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HD74LS93
4-bit Binary Counter
REJ03D0423-0200 Rev.2.00 Feb.18.2005 The HD74LS93 contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and three-state binary counter for divide-by-eight. To use this maximum count length of this counter, the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are described in the appropriate function table.
Features
* Ordering Information
Part Name HD74LS93P HD74LS93FPEL Package Type DILP-14 pin SOP-14 pin (JEITA) Package Code (Previous Code) PRDP0014AB-B (DP-14AV) PRSP0014DF-B (FP-14DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
B R0(1) R0(2) NC VCC NC NC
1 2 3 4 5 6 7 QC QB B R0(1) R0(2) A
14 13 QA QD 12 11 10 9 8
A NC QA QD GND QB QC
(Top view)
Rev.2.00, Feb.18.2005, page 1 of 8
HD74LS93
Function Table
* Reset / Count Function Table
Reset inputs R0(1) H L X Note: R0(2) H X L QD L QC L Count Count Outputs QB L QA L
H; high level, L; low level, X; irrelevant
* BCD Count Sequence (Notes 1)
Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 QD L L L L L L L L H H H H H H H H QC L L L L H H H H L L L L H H H H Outputs QB L L H H L L H H L L H H L L H H QA L H L H H H L H L H L H L H L H
Notes: 1. Output QA is connected to input B for BCD count. 2. H; high level, L; low level
Rev.2.00, Feb.18.2005, page 2 of 8
HD74LS93
Block Diagram
J Input A CK K J Input B CK K Q QB Q QA
J CK K
Q
QC
J CK K
Q
QD
R0(1) R0(2)
Absolute Maximum Ratings
Ratings 7 R Inputs 7 Input voltage A, B Inputs 5.5 Power dissipation PT 400 Storage temperature Tstg -65 to +150 Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Supply voltage Item Symbol VCC VIN VIN Unit V V V mW C
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature A input Count frequency B input A input Pulse width B input Reset input Setup time tsu Symbol VCC IOH IOL Topr fcount Min 4.75 -- -- -20 0 0 15 30 15 25 Typ 5.00 -- -- 25 -- -- -- -- -- -- Max 5.25 -400 8 75 32 16 -- -- -- -- Unit V A mA C MHz
tw
ns ns
Rev.2.00, Feb.18.2005, page 3 of 8
HD74LS93
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL Any reset A input B input Any reset A input B input Any reset A input B input Short-circuit output current Supply current Input clamp voltage IOS ICC*** VIK min. 2.0 -- 2.7 -- -- -- -- -- -- -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9 -- max. -- 0.8 -- 0.4 0.5 -0.4 -2.4 -1.6 20 40 40 0.1 0.2 0.2 -100 15 -1.5 mA mA V Unit V V V V Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA** VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA** VCC = 5.25 V, VI = 0.4 V
IIL
mA
Input current
IIH
A
VCC = 5.25 V, VI = 2.7 V VI = 7 V VI = 5.5 V VI = 5.5 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
II
mA
VCC = 5.25 V
Notes: * VCC = 5 V, Ta = 25C ** QA output is tested at specified IOL plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability. *** ICC is measured with all outputs open, both R0 inputs grounded following momentary connection to 4.5 V, and all other inputs grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum count frequency Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Inputs A B A A B B B Set-to-0 Outputs QA QB QA QD QB QC QD QA to QD min. 32 16 -- -- -- -- -- -- -- -- -- -- -- typ. 42 -- 10 12 46 46 10 14 21 23 34 34 26 max. -- -- 16 18 70 70 16 21 32 35 51 51 40 Unit MHz Condition
Propagation delay time
ns
CL = 15 pF, RL = 2 k
Note: Refer to Test Circuit and Waveform of the Common Item "TTL Common Matter (Document No.: REJ27D00050100)".
Rev.2.00, Feb.18.2005, page 4 of 8
HD74LS93
Timing Definition
tw 3V R0 1.3 V 1.3 V 0V tsu 3V A or B Input 1.3 V tw 1.3 V 0V
Testing Method
Test Circuit
VCC 4.5V Load circuit 1 QA
RL QA A B P.G. Zout = 50 CL QB QB QC R0 R0 QC QD QD
See Testing Table
Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1.
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Rev.2.00, Feb.18.2005, page 5 of 8
HD74LS93 Testing Table
Item fmax From input to output AQ BQ A QA A QD B QB B QC B QD R0** Q Inputs A IN 4.5 V IN IN 4.5 V 4.5 V 4.5 V IN* B to QA IN to QA to QA IN IN IN to QA R0 GND GND GND GND GND GND GND IN QA Out -- Out -- -- -- -- Out QB Out Out -- -- Out -- -- Out Outputs QC Out Out -- -- -- Out -- Out QD Out Out -- Out -- -- Out Out
tPLH tPHL
* For initialized. ** Measured with each input and unused inputs at 4.5 V.
Waveform 1. fmax, tPLH, tPHL (Clock Q)
tTLH tTHL 3V Clock 10% 90% 90% 1.3 V 10% tPHL(Measure at tn+2) QA 1.3 V tPHL (Measure at tn+4) QB 1.3 V VOL tPLH (Measure at tn+2) VOH 1.3 V tPHL (Measure at tn+8) 1.3 V tPLH (Measure at tn+4) VOL 1.3 V 0V tPLH (Measure at tn+1) VOH
VOH QC 1.3 V 1.3 V VOL
tPHL (Measure at tn+16) tPLH (Measure at tn+8)
VOH QD 1.3 V 1.3 V VOL
Notes:
1. Input pulse; tTLH 15 ns, tTHL 5 ns, PRR = 1 MHz, duty cycle = 50% and for fmax., tTLH = tTHL 2.5 ns 2. tn is reference bit time when all outputs are low.
Rev.2.00, Feb.18.2005, page 6 of 8
HD74LS93 2. tPHL (R0 Q)
tTLH tTHL 3V 10% tw 15ns tPHL VOH QA to QD 1.3 V VOL 0V
90% 90% 1.3 V 1.3 V R0 10%
Notes:
tTLH 15 ns, tTHL 5 ns
Rev.2.00, Feb.18.2005, page 7 of 8
HD74LS93
Package Dimensions
JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B Previous Code DP-14AV MASS[Typ.] 0.97g
D
14
8
1 b3
7
Z
E
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 2.39 2.54 0.56 Max
A
A1
e1 D E
L
A A1 bp
e
bp
e1
c
b3 c
e Z
( Ni/Pd/Au plating )
L
JEITA Package Code P-SOP14-5.5x10.06-1.27
RENESAS Code PRSP0014DF-B
Previous Code FP-14DAV
MASS[Typ.] 0.23g
*1
D 8
F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
14
bp
HE
E
Index mark
*2
c
Reference Symbol
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2 A1 0.00
7 bp x M L1
0.10
0.20 2.20
A bp b1 c c
1
0.34
0.40
0.46
0.15
0.20
0.25
A
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 1.42 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Feb.18.2005, page 8 of 8
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